Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET's

C. T. Chan*, C. J. Tang, Ta-Hui Wang, H. C.H. Wang, D. D. Tang

*此作品的通信作者

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

Positive bias and temperature (PBTI) stress induced drain current degradation in HfSiON gate dielectric nMOSFETs is investigated by using a transient measurement technique. The degradation exhibits two stages, featuring different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation. Process effect on high-k trap growth is evaluated.

原文English
主出版物標題IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
頁面563-566
頁數4
DOIs
出版狀態Published - 1 十二月 2005
事件IEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
持續時間: 5 十二月 20057 十二月 2005

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2005
ISSN(列印)0163-1918

Conference

ConferenceIEEE International Electron Devices Meeting, 2005 IEDM
國家/地區United States
城市Washington, DC, MD
期間5/12/057/12/05

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