Pole-aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire-Crossings

Abhishek Patyal, Hung Ming Chen, Po-Hung Lin, Guan Qi Fang, Simon Yi Hung Chen

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)


This paper presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry-island and monotonic current flow while minimizing wire-crossings. The nodes along the signal paths in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placement methods introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially the dominant and the first non-dominant poles and wire-crossings among critical nets, may increase wire-load and performance degradation. This paper proposes a pole-aware analog layout synthesis methodology to minimize the total wire load and wire-crossings while satisfying different symmetry and topological routing constraints. Using a strong-connectivity approach to the group Steiner problem, the presented method for automatic selection of port locations can help reduce total wirelength, increase routing flexibility, and minimize total wire-crossings. Experimental results show that the proposed approach results in better solution quality in circuit performance compared with other recent works.

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期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
出版狀態Accepted/In press - 2022


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