Plate-Noise Analysis of an On-Chip Generated Half-VDD Biased-Plate PMOS Cell in CMOS DRAM's

Nicky C.C. Lu, Hu H. Chao, Wei Hwang

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)

摘要

This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described.

原文English
頁(從 - 到)1272-1276
頁數5
期刊IEEE Journal of Solid-State Circuits
20
發行號6
DOIs
出版狀態Published - 1 1月 1985

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