Pipelining technique for energy-aware datapaths

Wei Sheng Huang*, Tay Jyi Lin, Shih Hao Ou, Chih-Wei Liu, Chein Wei Jen

*此作品的通信作者

    研究成果: Conference article同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a novel method to improve the energy awareness of the pipelined datapaths for varying throughputs. It activates the pipeline registers only when necessary; i.e. a data item can bypass the pipeline registers when the operation is free of race from the succeeding one, and when the glitch is minimal. Then, the clock pulses of the unused pipeline registers are gated to reduce the energy dissipation. Compared to the conventional clock gating approach, our proposed on-demand pipelining eliminates all redundant clock pulses whenever the peak datarate is not reached. Moreover, our method has a constant input-tooutput latency for all operation modes, which significantly simplifies the integration tasks. In our simulations, the proposed on-demand pipelining saves up to 80% energy of conventional pipelined datapaths, and it can reduce about 34%̃39% energy dissipation of those with gated-clock only.

    原文English
    文章編號1464813
    頁(從 - 到)1218-1221
    頁數4
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    DOIs
    出版狀態Published - 2005
    事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, 日本
    持續時間: 23 5月 200526 5月 2005

    指紋

    深入研究「Pipelining technique for energy-aware datapaths」主題。共同形成了獨特的指紋。

    引用此