Pipelined multiplier-accumulator using a high speed, low power static and dynamic full adder design

Shyh-Jye Jou; Chang Yu Chen; En Chung Yang; Chau-Chin Su

Pipelined multiplier-accumulator using a high speed, low power static and dynamic full adder design

Shyh-Jye Jou^*, Chang Yu Chen, En Chung Yang, Chau-Chin Su

^*此作品的通信作者

研究成果: Conference article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A new full-adder circuit for pipeline architecture is proposed. Compared with other full-adder circuits, it has high operational speed smallest transistor number and the lowest power/speed ratio. This new full-adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In the MAC, a special pipelined structure is designed to reduce the latency. The whole chip is fabricated in a 0.8 μm Single-Poly-Double-Metal CMOS process and the post-layout simulation of the pipelined 1-bit full adder can work up to 350 MHz. The whole chip which contains 4200 transistor are measured to operate at 125 MHz using 3.3 V power supply.

原文	English
文章編號	5486845
頁（從 - 到）	593-596
頁數	4
期刊	Proceedings of the Custom Integrated Circuits Conference
卷	32
發行號	1
出版狀態	Published - 1 1月 1995
事件	Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA 持續時間: 1 5月 1995 → 4 5月 1995

其它文件與鏈接

Link to publication in Scopus

引用此

@article{ef3f8d359a8e4290a8feb7cc08e75af5,

title = "Pipelined multiplier-accumulator using a high speed, low power static and dynamic full adder design",

abstract = "A new full-adder circuit for pipeline architecture is proposed. Compared with other full-adder circuits, it has high operational speed smallest transistor number and the lowest power/speed ratio. This new full-adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In the MAC, a special pipelined structure is designed to reduce the latency. The whole chip is fabricated in a 0.8 μm Single-Poly-Double-Metal CMOS process and the post-layout simulation of the pipelined 1-bit full adder can work up to 350 MHz. The whole chip which contains 4200 transistor are measured to operate at 125 MHz using 3.3 V power supply.",

author = "Shyh-Jye Jou and Chen, {Chang Yu} and Yang, {En Chung} and Chau-Chin Su",

year = "1995",

month = jan,

day = "1",

language = "English",

volume = "32",

pages = "593--596",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

note = "Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference ; Conference date: 01-05-1995 Through 04-05-1995",

}

TY - JOUR

T1 - Pipelined multiplier-accumulator using a high speed, low power static and dynamic full adder design

AU - Jou, Shyh-Jye

AU - Chen, Chang Yu

AU - Yang, En Chung

AU - Su, Chau-Chin

PY - 1995/1/1

Y1 - 1995/1/1

N2 - A new full-adder circuit for pipeline architecture is proposed. Compared with other full-adder circuits, it has high operational speed smallest transistor number and the lowest power/speed ratio. This new full-adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In the MAC, a special pipelined structure is designed to reduce the latency. The whole chip is fabricated in a 0.8 μm Single-Poly-Double-Metal CMOS process and the post-layout simulation of the pipelined 1-bit full adder can work up to 350 MHz. The whole chip which contains 4200 transistor are measured to operate at 125 MHz using 3.3 V power supply.

AB - A new full-adder circuit for pipeline architecture is proposed. Compared with other full-adder circuits, it has high operational speed smallest transistor number and the lowest power/speed ratio. This new full-adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In the MAC, a special pipelined structure is designed to reduce the latency. The whole chip is fabricated in a 0.8 μm Single-Poly-Double-Metal CMOS process and the post-layout simulation of the pipelined 1-bit full adder can work up to 350 MHz. The whole chip which contains 4200 transistor are measured to operate at 125 MHz using 3.3 V power supply.

UR - http://www.scopus.com/inward/record.url?scp=0029236594&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029236594

SN - 0886-5930

VL - 32

SP - 593

EP - 596

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

IS - 1

M1 - 5486845

T2 - Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference

Y2 - 1 May 1995 through 4 May 1995

ER -

Pipelined multiplier-accumulator using a high speed, low power static and dynamic full adder design

摘要

其它文件與鏈接

指紋

引用此