A new full-adder circuit for pipeline architecture is proposed. Compared with other full-adder circuits, it has high operational speed smallest transistor number and the lowest power/speed ratio. This new full-adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In the MAC, a special pipelined structure is designed to reduce the latency. The whole chip is fabricated in a 0.8 μm Single-Poly-Double-Metal CMOS process and the post-layout simulation of the pipelined 1-bit full adder can work up to 350 MHz. The whole chip which contains 4200 transistor are measured to operate at 125 MHz using 3.3 V power supply.
|頁（從 - 到）||593-596|
|期刊||Proceedings of the Custom Integrated Circuits Conference|
|出版狀態||Published - 1 1月 1995|
|事件||Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA|
持續時間: 1 5月 1995 → 4 5月 1995