Pin accessibility evaluating model for improving routability of VLSI designs

Hong Yan Su, Shinichi Nishizawa, Yan Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.

原文English
主出版物標題Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017
編輯Jurgen Becker, Ramalingam Sridhar, Hai Li, Ulf Schlichtmann, Massimo Alioto
發行者IEEE Computer Society
頁面56-61
頁數6
ISBN(電子)9781538640333
DOIs
出版狀態Published - 18 12月 2017
事件30th IEEE International System on Chip Conference, SOCC 2017 - Munich, Germany
持續時間: 5 9月 20178 9月 2017

出版系列

名字International System on Chip Conference
2017-September
ISSN(列印)2164-1676
ISSN(電子)2164-1706

Conference

Conference30th IEEE International System on Chip Conference, SOCC 2017
國家/地區Germany
城市Munich
期間5/09/178/09/17

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