Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy

Kang Yi Fan, Jyun Hua Chen, Chien Nan Liu, Juinn Dar Huang

研究成果: Conference contribution同行評審

摘要

It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation strategy that can maximize the overall performance. Experiment results show that the proposed strategy constantly outperforms several trivial heuristic methods over a large set of various MLP models, MLP accelerator configurations, and on-chip SRAM capacities.

原文English
主出版物標題2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665409216
DOIs
出版狀態Published - 2022
事件2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, Taiwan
持續時間: 18 4月 202221 4月 2022

出版系列

名字2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
國家/地區Taiwan
城市Hsinchu
期間18/04/2221/04/22

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