TY - GEN
T1 - Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor
AU - Huang, Po Chun
AU - Sheu, Tzu Shiun
AU - Chen, Chen Chia
AU - Chen, Lu An
AU - Sheu, Jeng-Tzong
PY - 2008/6/15
Y1 - 2008/6/15
N2 -
In this work, performance of dual-channel GAA poly-Si nanowire TFT with NH
3
plasma passivation was demonstrated. The proposed devices exhibit low leakage current in off state, a high I
on
/I
off
current ratio, a low subthreshold slope, an absence of DIBL and promising output characteristics. It is believed that this high performance poly-Si TFT is suitable for future applications.
AB -
In this work, performance of dual-channel GAA poly-Si nanowire TFT with NH
3
plasma passivation was demonstrated. The proposed devices exhibit low leakage current in off state, a high I
on
/I
off
current ratio, a low subthreshold slope, an absence of DIBL and promising output characteristics. It is believed that this high performance poly-Si TFT is suitable for future applications.
UR - http://www.scopus.com/inward/record.url?scp=77949963636&partnerID=8YFLogxK
U2 - 10.1109/SNW.2008.5418415
DO - 10.1109/SNW.2008.5418415
M3 - Conference contribution
AN - SCOPUS:77949963636
SN - 9781424420711
T3 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
T2 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
Y2 - 15 June 2008 through 16 June 2008
ER -