Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

Chia Chen Lin; Yi Jui Wu; Wei Xiang You; Pin Su

doi:10.1109/VLSI-TSA48913.2020.9203647

Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

Chia Chen Lin, Yi Jui Wu, Wei Xiang You, Pin Su^*

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

原文	English
主出版物標題	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	62-63
頁數	2
ISBN（電子）	9781728142326
DOIs	https://doi.org/10.1109/VLSI-TSA48913.2020.9203647
出版狀態	Published - 8月 2020
事件	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, 台灣持續時間: 10 8月 2020 → 13 8月 2020

出版系列

名字	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
國家/地區	台灣
城市	Hsinchu
期間	10/08/20 → 13/08/20

存取文件

10.1109/VLSI-TSA48913.2020.9203647

其它文件與鏈接

Link to publication in Scopus

引用此

Lin, C. C., Wu, Y. J., You, W. X., & Su, P. (2020). Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 (頁 62-63). 文章 9203647 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA48913.2020.9203647

Lin, Chia Chen ; Wu, Yi Jui ; You, Wei Xiang 等. / Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 頁 62-63 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

@inproceedings{da4815ef25b0410882d639a779a559c7,

title = "Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers",

abstract = "In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).",

author = "Lin, {Chia Chen} and Wu, {Yi Jui} and You, {Wei Xiang} and Pin Su",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 ; Conference date: 10-08-2020 Through 13-08-2020",

year = "2020",

month = aug,

doi = "10.1109/VLSI-TSA48913.2020.9203647",

language = "English",

series = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "62--63",

booktitle = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

address = "美國",

}

Lin, CC, Wu, YJ, You, WX & Su, P 2020, Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020., 9203647, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Institute of Electrical and Electronics Engineers Inc., 頁 62-63, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Hsinchu, 台灣, 10/08/20. https://doi.org/10.1109/VLSI-TSA48913.2020.9203647

Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. / Lin, Chia Chen; Wu, Yi Jui; You, Wei Xiang 等.
2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 62-63 9203647 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

AU - Lin, Chia Chen

AU - Wu, Yi Jui

AU - You, Wei Xiang

AU - Su, Pin

PY - 2020/8

Y1 - 2020/8

N2 - In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

AB - In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

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U2 - 10.1109/VLSI-TSA48913.2020.9203647

DO - 10.1109/VLSI-TSA48913.2020.9203647

M3 - Conference contribution

AN - SCOPUS:85093646039

T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

SP - 62

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BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

PB - Institute of Electrical and Electronics Engineers Inc.

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Lin CC, Wu YJ, You WX, Su P. Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 62-63. 9203647. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). doi: 10.1109/VLSI-TSA48913.2020.9203647

Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

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