Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay

Juinn-Dar Huang*, Chia I. Chen, Wan Ling Hsu, Yen Ting Lin, Jing Yang Jou

*此作品的通信作者

    研究成果: Conference contribution同行評審

    4 引文 斯高帕斯(Scopus)

    摘要

    In deep-submicron era, wire delay is becoming the bottleneck while pursuing high system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this paper, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). With such delay consideration, synthesis task is inherently more complicated than the one with no inter-island delay concern since uncertain interconnect latency is very likely to make a serious impact on whole system performance. Hence we also develop a performance-driven architectural synthesis framework targeting DRFM-IID, which takes the number of inter-island transfers, transfer criticality and resource utilization into account for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is a common indicator for power consumption of on-chip communication.

    原文English
    主出版物標題Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
    頁面169-172
    頁數4
    DOIs
    出版狀態Published - 8 11月 2010
    事件2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, 台灣
    持續時間: 26 4月 201029 4月 2010

    出版系列

    名字Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

    Conference

    Conference2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
    國家/地區台灣
    城市Hsin Chu
    期間26/04/1029/04/10

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