Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.
|頁（從 - 到）||613-619|
|期刊||IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD|
|出版狀態||Published - 1 十二月 2012|
|事件||2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States|
持續時間: 5 十一月 2012 → 8 十一月 2012