Performance-driven analog placement considering monotonic current paths

Po Hsun Wu*, Po-Hung Lin, Yang Ru Chen, Bing Shiun Chou, Tung Chieh Chen, Tsung Yi Ho, Bin Da Liu

*此作品的通信作者

研究成果: Conference article同行評審

18 引文 斯高帕斯(Scopus)

摘要

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.

原文English
文章編號6386735
頁(從 - 到)613-619
頁數7
期刊IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
DOIs
出版狀態Published - 1 十二月 2012
事件2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States
持續時間: 5 十一月 20128 十一月 2012

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