Passive reduced-order macro-modeling for linear time-delay interconnect systems

Wenliang Tseng; Chien-Nan Liu; Chau-Chin Su

doi:10.1093/ietele/e89-c.11.1713

Passive reduced-order macro-modeling for linear time-delay interconnect systems

Wenliang Tseng^*, Chien-Nan Liu, Chau-Chin Su

^*此作品的通信作者

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.

原文	English
頁（從 - 到）	1713-1718
頁數	6
期刊	IEICE Transactions on Electronics
卷	E89-C
發行號	11
DOIs	https://doi.org/10.1093/ietele/e89-c.11.1713
出版狀態	Published - 11月 2006

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10.1093/ietele/e89-c.11.1713

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引用此

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KW - Passive macromodels

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Passive reduced-order macro-modeling for linear time-delay interconnect systems

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