Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling dac

Po-Hung Lin, Vincent Wei Hao Hsiao, Chun Yu Lin

研究成果: Conference contribution同行評審

19 引文 斯高帕斯(Scopus)

摘要

Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the rst problem formula-tion in the literature which simultaneously considers capac-itor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consump-tion is minimized while the circuit accuracy/performance is also satised. Experimental results show that the proposed approach can achieve very signicant chip area and power reductions compared with the state of the art.

原文English
主出版物標題DAC 2014 - 51st Design Automation Conference, Conference Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)9781479930173
DOIs
出版狀態Published - 1 一月 2014
事件51st Annual Design Automation Conference, DAC 2014 - San Francisco, CA, United States
持續時間: 2 六月 20145 六月 2014

出版系列

名字Proceedings - Design Automation Conference
ISSN(列印)0738-100X

Conference

Conference51st Annual Design Automation Conference, DAC 2014
國家/地區United States
城市San Francisco, CA
期間2/06/145/06/14

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