Parasitic-aware common-centroid FinFET placement and routing for current-ratio matching

Po Hsun Wu, Po-Hung Lin, Xin Li, Tsung Yi Ho

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from process variation and the parasitic resistance resulting from interconnecting wires based on the FinFET technology becomes evenmore severe compared with the conventional planar CMOS technology. Such gate misalignment and unwanted parasitic resistance may increase the threshold voltage and decrease the drain current of transistors. When applying the FinFET technology to analog circuit design, the variation of drain currents can destroy current-ratio matching among transistors and degrade circuit performance. In this article, we present the first FinFET placement and routing algorithms for layout generation of a common-centroid FinFET array to precisely match the current ratios among transistors. Experimental results show that the proposed matching-driven FinFET placement and routing algorithms can obtain the best current-ratio matching compared with the state-of-the-art common-centroid placer.

原文English
文章編號39
期刊ACM Transactions on Design Automation of Electronic Systems
21
發行號3
DOIs
出版狀態Published - 1 四月 2016

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