Parameterized and low power DSP core for embedded systems

Ya Lan Tsao*, Ming Hsuan Tan, Jun Xian Teng, Shyh-Jye Jou

*此作品的通信作者

研究成果: Conference article同行評審

5 引文 斯高帕斯(Scopus)

摘要

Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (GUI) and can generate synthesizable verilog code of the embedded DSP core according to user's specification.

原文English
頁(從 - 到)V265-V268
期刊Proceedings - IEEE International Symposium on Circuits and Systems
5
DOIs
出版狀態Published - 2003
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 25 5月 200328 5月 2003

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