Parallelism of circuit simulation on array processor

Shyh-Jye Jou; Chein Wei Jen; Wen Zen Shen

doi:10.1109/ISCAS.1991.176109

Parallelism of circuit simulation on array processor

Shyh-Jye Jou^*, Chein Wei Jen, Wen Zen Shen

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

摘要

The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.

原文	English
頁（從 - 到）	2725-2728
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	5
DOIs	https://doi.org/10.1109/ISCAS.1991.176109
出版狀態	Published - 1 12月 1991
事件	1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore 持續時間: 11 6月 1991 → 14 6月 1991

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10.1109/ISCAS.1991.176109

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title = "Parallelism of circuit simulation on array processor",

abstract = "The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.",

author = "Shyh-Jye Jou and Jen, {Chein Wei} and Shen, {Wen Zen}",

year = "1991",

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T1 - Parallelism of circuit simulation on array processor

AU - Jou, Shyh-Jye

AU - Jen, Chein Wei

AU - Shen, Wen Zen

PY - 1991/12/1

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N2 - The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.

AB - The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.

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U2 - 10.1109/ISCAS.1991.176109

DO - 10.1109/ISCAS.1991.176109

M3 - Conference article

AN - SCOPUS:0026390793

SN - 0271-4310

VL - 5

SP - 2725

EP - 2728

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 11 June 1991 through 14 June 1991

ER -

Parallelism of circuit simulation on array processor

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