TY - JOUR
T1 - Parallelism of circuit simulation on array processor
AU - Jou, Shyh-Jye
AU - Jen, Chein Wei
AU - Shen, Wen Zen
PY - 1991
Y1 - 1991
N2 - The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.
AB - The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.
UR - http://www.scopus.com/inward/record.url?scp=0026390793&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.1991.176109
DO - 10.1109/ISCAS.1991.176109
M3 - Conference article
AN - SCOPUS:0026390793
SN - 0271-4310
VL - 5
SP - 2725
EP - 2728
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - 1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5)
Y2 - 11 June 1991 through 14 June 1991
ER -