The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.
|頁（從 - 到）||2725-2728|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 12月 1991|
|事件||1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore|
持續時間: 11 6月 1991 → 14 6月 1991