Parallel subcircuit extraction algorithm on GPGPUs

Che Lun Hung, Hsiao Hsi Wang, Chun Ting Fu, Chia Shin Ou

研究成果: Conference contribution同行評審

摘要

Subcircuit Extraction plays an important role in Computer-Aided-Design of digital circuits. With the rapid growth of wafer processing technologies, the integration is from very large scale to giga large scale. Therefore, to extract sub circuits from such large scale integration is computation-consuming problem. In this paper, we propose a parallel sub circuit extraction algorithm on graphic processing unit. The experimental result shows that the proposed algorithm can achieve over 3x-7x times faster than serial algorithm.

原文English
主出版物標題Proceedings - 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1248-1252
頁數5
ISBN(電子)9781479961238
DOIs
出版狀態Published - 9 3月 2014
事件16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014 - Paris, France
持續時間: 20 8月 201422 8月 2014

出版系列

名字Proceedings - 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014

Conference

Conference16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014
國家/地區France
城市Paris
期間20/08/1422/08/14

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