Parallel Scrambler for High-Speed Applications

Chih Hsien Lin; Chih Ning Chen; You Jiun Wang; Ju Yuan Hsiac; Shyh-Jye Jou

doi:10.1109/TCSII.2006.875316

Parallel Scrambler for High-Speed Applications

Chih Hsien Lin, Chih Ning Chen, You Jiun Wang, Ju Yuan Hsiac, Shyh-Jye Jou

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

摘要

In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

原文	English
頁（從 - 到）	558-562
頁數	5
期刊	IEEE Transactions on Circuits and Systems I: Regular Papers
卷	53
發行號	7
DOIs	https://doi.org/10.1109/TCSII.2006.875316
出版狀態	Published - 6 7月 2006

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AU - Lin, Chih Hsien

AU - Chen, Chih Ning

AU - Wang, You Jiun

AU - Hsiac, Ju Yuan

AU - Jou, Shyh-Jye

PY - 2006/7/6

Y1 - 2006/7/6

N2 - In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

AB - In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

KW - Parallel scrambler

KW - register

KW - XOR

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Parallel Scrambler for High-Speed Applications

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