Parallel Scrambler for High-Speed Applications

Chih Hsien Lin, Chih Ning Chen, You Jiun Wang, Ju Yuan Hsiac, Shyh-Jye Jou

    研究成果: Article同行評審

    12 引文 斯高帕斯(Scopus)

    摘要

    In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

    原文English
    頁(從 - 到)558-562
    頁數5
    期刊IEEE Transactions on Circuits and Systems I: Regular Papers
    53
    發行號7
    DOIs
    出版狀態Published - 6 7月 2006

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