Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

Minchen Chang; Jengping Lin; Ruey Dar Chang; Steven N. Shih; Chao Sung Lai; Pei Ing Lee

Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

Minchen Chang^*, Jengping Lin, Ruey Dar Chang, Steven N. Shih, Chao Sung Lai, Pei Ing Lee

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1 引文斯高帕斯（Scopus）

摘要

The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.

原文	English
頁面	307-310
頁數	4
出版狀態	Published - 2004
事件	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , 台灣持續時間: 5 7月 2004 → 8 7月 2004

Conference

Conference	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
國家/地區	台灣
期間	5/07/04 → 8/07/04

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@conference{eeebc1bc661b44f086c5df175170f441,

title = "Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias",

abstract = "The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.",

author = "Minchen Chang and Jengping Lin and Chang, {Ruey Dar} and Shih, {Steven N.} and Lai, {Chao Sung} and Lee, {Pei Ing}",

year = "2004",

language = "English",

pages = "307--310",

note = "Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 ; Conference date: 05-07-2004 Through 08-07-2004",

}

TY - CONF

T1 - Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

AU - Chang, Minchen

AU - Lin, Jengping

AU - Chang, Ruey Dar

AU - Shih, Steven N.

AU - Lai, Chao Sung

AU - Lee, Pei Ing

PY - 2004

Y1 - 2004

N2 - The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.

AB - The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.

UR - http://www.scopus.com/inward/record.url?scp=14844288338&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:14844288338

SP - 307

EP - 310

T2 - Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004

Y2 - 5 July 2004 through 8 July 2004

ER -

Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

摘要

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