PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays

Chien-Chihh Huang, Jwu E. Chen, Chin-Long Wey

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

Capacitor matching influences linearity performance, which is a critical measure of analog-to-digital converters (ADCs). Various placement techniques have been proposed to eliminate both systematic and random mismatches of capacitor pairs. However, a placement technique that eliminates capacitor mismatches may not result in good linearity performance for successive-approximation-register ADCs because their linearity performance is related to the accuracy of their binary-weighted continued ratio. This paper addresses the critical problem of placement estimation based on ratio mismatch M, overall correlation coefficient L, and performance metrics. A low M and a high L value do not imply higher linearity performance. Therefore, we propose a partition-centering-based symmetry placement algorithm for the layout considering parasitic capacitance matching. The experimental results show that the proposed placement approach can achieve higher linearity performance and a shorter placement generation time compared with the conventional approach.
原文English
頁(從 - 到)134-145
頁數12
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
36
發行號1
DOIs
出版狀態Published - 一月 2017

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