Overview on Latch-up Prevention in CMOS Integrated Circuits by Circuit Solutions

Ming Dou Ker, Zi Hong Jiang

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed.

原文English
頁(從 - 到)1
頁數1
期刊IEEE Journal of the Electron Devices Society
DOIs
出版狀態Accepted/In press - 2022

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