Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Woei Cherng Wu*, Tien-Sheng Chao, Wu Chin Peng, Wen Luh Yang, Jian Hao Chen, Ming Wen Ma, Chao Sung Lai, Tsung Yu Yang, Chien Hsing Lee, Tsung Min Hsieh, Jhyy Cheng Liou, Tzu Ping Chen, Chien Hung Chen, Chih Hung Lin, Hwi Huang Chen, Joe Ko

*此作品的通信作者

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 νs/5 ms) and low programming current (3.5 νA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

原文English
文章編號015004
期刊Semiconductor Science and Technology
23
發行號1
DOIs
出版狀態Published - 1 1月 2008

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