Optimized layout on ESD protection diode with low parasitic capacitance

Keyphrases

• 90-nm CMOS Technology 33%
• Biased Conditions 33%
• CMOS Integrated Circuits 33%
• CMOS Process 33%
• Diode 33%
• Electrostatic Discharge 33%
• Electrostatic Discharge (ESD) Protection 100%
• Hollow 33%
• Layout Optimization 100%
• Loading Effect 33%
• Low Parasitic Capacitance 100%
• On chip 33%
• Parasitic Load 33%
• Protection Device 33%
• Protection Diodes 100%
• Waffle 66%
• Waffle Layout 33%

Material Science

• Capacitance 100%
• Electronic Circuit 100%

Physics

• Electrostatics 100%
• Integrated Circuit 25%