Optimized layout on ESD protection diode with low parasitic capacitance

Chih Ting Yeh*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.

    原文English
    主出版物標題ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
    頁面1701-1703
    頁數3
    DOIs
    出版狀態Published - 1 12月 2010
    事件2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
    持續時間: 1 11月 20104 11月 2010

    出版系列

    名字ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

    Conference

    Conference2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
    國家/地區China
    城市Shanghai
    期間1/11/104/11/10

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