TY - GEN
T1 - Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology
AU - Chen, Shin Hung
AU - Ker, Ming-Dou
PY - 2008
Y1 - 2008
N2 - NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
AB - NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
UR - http://www.scopus.com/inward/record.url?scp=57849107755&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2008.4674941
DO - 10.1109/ICECS.2008.4674941
M3 - Conference contribution
AN - SCOPUS:57849107755
SN - 9781424421824
T3 - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
SP - 666
EP - 669
BT - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
T2 - 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Y2 - 31 August 2008 through 3 September 2008
ER -