Optimization on layout style of ESD protection diode for radio-frequency front-end and high-speed I/O interface circuits

Chih Ting Yeh*, Ming-Dou Ker, Yung Chih Liang

*此作品的通信作者

    研究成果: Article同行評審

    27 引文 斯高帕斯(Scopus)

    摘要

    The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.

    原文English
    文章編號5415645
    頁(從 - 到)238-246
    頁數9
    期刊IEEE Transactions on Device and Materials Reliability
    10
    發行號2
    DOIs
    出版狀態Published - 6月 2010

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