Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin; Mei Lian Fan

doi:10.1109/TDMR.2014.2311130

Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin, Mei Lian Fan

電子研究所

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

摘要

The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V_DD or lower than V_SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

原文	English
文章編號	6763105
頁（從 - 到）	775-777
頁數	3
期刊	IEEE Transactions on Device and Materials Reliability
卷	14
發行號	2
DOIs	https://doi.org/10.1109/TDMR.2014.2311130
出版狀態	Published - 6月 2014

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10.1109/TDMR.2014.2311130

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abstract = "The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.",

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AB - The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

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Optimization on layout style of diode stackup for on-chip ESD protection

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