Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

Shin Hung Chen; Ming-Dou Ker

doi:10.1109/IPFA.2007.4378093

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

Shin Hung Chen^*, Ming-Dou Ker

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

原文	English
主出版物標題	Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
頁面	245-248
頁數	4
DOIs	https://doi.org/10.1109/IPFA.2007.4378093
出版狀態	Published - 1 12月 2007
事件	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India 持續時間: 11 7月 2007 → 13 7月 2007

出版系列

名字	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
國家/地區	India
城市	Bangalore
期間	11/07/07 → 13/07/07

存取文件

10.1109/IPFA.2007.4378093

其它文件與鏈接

Link to publication in Scopus

引用此

Chen, S. H., & Ker, M.-D. (2007). Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. 於 Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007 (頁 245-248). 文章 4378093 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2007.4378093

Chen, Shin Hung ; Ker, Ming-Dou. / Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. 頁 245-248 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{19b30b0876d34a33aac19e3e43887dfd,

title = "Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology",

abstract = "PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.",

author = "Chen, {Shin Hung} and Ming-Dou Ker",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/IPFA.2007.4378093",

language = "English",

isbn = "1424410142",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

pages = "245--248",

booktitle = "Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007",

note = "2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits ; Conference date: 11-07-2007 Through 13-07-2007",

}

Chen, SH & Ker, M-D 2007, Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. 於 Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007., 4378093, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 頁 245-248, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Bangalore, India, 11/07/07. https://doi.org/10.1109/IPFA.2007.4378093

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. / Chen, Shin Hung; Ker, Ming-Dou.
Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 245-248 4378093 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

研究成果: Conference contribution › 同行評審

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N2 - PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

AB - PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

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Chen SH, Ker MD. Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. 於 Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 245-248. 4378093. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2007.4378093

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

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