Optimization of placement solutions for routability

Wen Hao Liu, Cheng Kok Koh, Yih-Lang Li

研究成果: Conference contribution同行評審

33 引文 斯高帕斯(Scopus)


Routability has become a critical issue in VLSI design flow. To avoid producing an unroutable design, many placers [4- 7] invoke global routers to get a congestion map and then move cells to reduce congestion based on this map. However, as cells move, the accuracy of the congestion map degrades, thereby affecting the effectiveness of the placer in minimizing congestions. Moreover, most global routers [8-13] ignore local congestion. If placers are guided by these routers, it may produce hard-to-route placement solutions in terms of detailed routing. This work develops a routability optimizer, called Ropt, to reduce both global and local routing congestion levels of a given placement. Based on a local-routability-aware routing model, Ropt builds a global routing instance to obtain global and local congestion information for guiding global re-placement. In addition, this work presents a new legalization scheme to preserve the global routing instance after legalization. Finally, local detailed placement further minimizes the local congestion and wirelength. For the evaluation of Ropt, we use an academic global router and a commercial router to obtain both global and detailed routing results, respectively. Experimental results reveal that Ropt can improve the routing quality (in terms of congestion, wirelength, and violation) and routing runtime of a given placement solution. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids - Placement and Routing. General Terms Algorithms, Design.

主出版物標題Proceedings of the 50th Annual Design Automation Conference, DAC 2013
出版狀態Published - 12 7月 2013
事件50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
持續時間: 29 5月 20137 6月 2013


名字Proceedings - Design Automation Conference


Conference50th Annual Design Automation Conference, DAC 2013
國家/地區United States
城市Austin, TX


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