Optimization of Gate Oxide N2O Anneal for CMOSFET’s at Room and Cryogenic Temperatures

Zhi Jian Ma, Ping K. Ko, Chen-Ming Hu, H. J. Huang

研究成果: Article同行評審

27 引文 斯高帕斯(Scopus)

摘要

This paper presents a study of the impact of gate- oxide N20 anneal on CMOSFET’s characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 A) and five N20 anneal conditions (900 ~ 950°C, 5 ~ 40 min) plus nonnitrided process and channel lengths from 0.2 to 2 ±m were studied to establish the correlation between the nitrogen concentration at Si/SiO2 interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N20 anneal step can increase CMOSFET’s lifetime by 4 ~ 10 times, effectively suppress boron penetration from the P+ poly-Si gate of P-MOSFET’s without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO2 interface. The optimal N20 anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO2 interface which can be realized by annealing 60 ~ 110 A oxides at 950° C for 5 min or 900° C for 20 min.

原文English
頁(從 - 到)1364-1372
頁數9
期刊IEEE Transactions on Electron Devices
41
發行號8
DOIs
出版狀態Published - 1 一月 1994

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