ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design

Samuel Liu, Jen Ho Kuo, Luba Tang, Ning Chi Huang, Der Yu Tsai, M. H. Yang, Kai Chiang Wu

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

The calculation of the convolution is considered the most important part in convolutional neural network-based artificial intelligence (AI) deep learning accelerator (DLA) architecture. Regardless of employing the traditional von Neumann architecture or the non-von Neumann compute-in-memory architecture, the variations arising from the integrated circuit (IC) process at the mass production stage must be considered. The AI model accuracy also needs to be improved. The open neural network compiler (ONNC) is an architecture-aware AI software development kit toolchain, which is capable of evaluating the AI model on fixed-point Edge AI DLAs for the open neural network exchange model. In this paper, the ONNC toolchain and the NVIDIA DLA (NVDLA) field-programmable gate array are employed to investigate the NVDLA static random-access memory stuck-at fault impact on model accuracy. The fault-mitigating results after applying a recovery mechanism in the IC process hard failure are also discussed.A method for utilizing the ONNC framework and the recovery guidelines for the resistive random-access memory -based computer-integrated manufacturing DLA architecture is also proposed.

原文English
主出版物標題2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665419154
DOIs
出版狀態Published - 19 4月 2021
事件2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, 台灣
持續時間: 19 4月 202122 4月 2021

出版系列

名字2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

Conference

Conference2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
國家/地區台灣
城市Hsinchu
期間19/04/2122/04/21

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