摘要
We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.
原文 | English |
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頁面 | 15-20 |
頁數 | 6 |
DOIs | |
出版狀態 | Published - 4月 2004 |
事件 | Proceedings of the IEEE Radar Conference - Philadelphia, PA, United States 持續時間: 26 4月 2004 → 29 4月 2004 |
Conference
Conference | Proceedings of the IEEE Radar Conference |
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國家/地區 | United States |
城市 | Philadelphia, PA |
期間 | 26/04/04 → 29/04/04 |