In this transactions letter, an innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation. Having these features, the selective coefficient DCT core will fit for various area/speed requirements. It can save the transposition delay to simplify the computation flow of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient.
|頁（從 - 到）||143-146|
|期刊||IEEE Transactions on Circuits and Systems for Video Technology|
|出版狀態||Published - 四月 1998|