On the design of selective coefficient DCT module

Chung Yen Lu; Kuei-Ann Wen

doi:10.1109/76.664099

On the design of selective coefficient DCT module

Chung Yen Lu^*, Kuei-Ann Wen

^*此作品的通信作者

電子工程學系

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

摘要

In this transactions letter, an innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation. Having these features, the selective coefficient DCT core will fit for various area/speed requirements. It can save the transposition delay to simplify the computation flow of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient.

原文	English
文章編號	5887647
頁（從 - 到）	143-146
頁數	4
期刊	IEEE Transactions on Circuits and Systems for Video Technology
卷	8
發行號	2
DOIs	https://doi.org/10.1109/76.664099
出版狀態	Published - 四月 1998

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On the design of selective coefficient DCT module

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