摘要
In this transactions letter, an innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation. Having these features, the selective coefficient DCT core will fit for various area/speed requirements. It can save the transposition delay to simplify the computation flow of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient.
原文 | English |
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文章編號 | 5887647 |
頁(從 - 到) | 143-146 |
頁數 | 4 |
期刊 | IEEE Transactions on Circuits and Systems for Video Technology |
卷 | 8 |
發行號 | 2 |
DOIs | |
出版狀態 | Published - 4月 1998 |