On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ming-Dou Ker*, Po Yen Chiu, Fu Yi Tsai, Yeong Jar Chang

*此作品的通信作者

    研究成果: Conference contribution › 同行評審

    15 引文 斯高帕斯（Scopus）

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    Engineering & Materials Science