On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ming-Dou Ker*, Po Yen Chiu, Fu Yi Tsai, Yeong Jar Chang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    15 引文 斯高帕斯(Scopus)

    摘要

    A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25°C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.

    原文English
    主出版物標題2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
    頁面2281-2284
    頁數4
    DOIs
    出版狀態Published - 2009
    事件2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
    持續時間: 24 5月 200927 5月 2009

    出版系列

    名字Proceedings - IEEE International Symposium on Circuits and Systems
    ISSN(列印)0271-4310

    Conference

    Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
    國家/地區Taiwan
    城市Taipei
    期間24/05/0927/05/09

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