On Reliability Hardening of FPGA based RO-PUF by using Regression Methodologies

A. K. Asha, Abhishek Patyal, Hung Ming Chen

研究成果: Conference contribution同行評審

摘要

Physical Unclonable Function (PUF) is a rapidly growing hardware security primitive. In reconfigurable systems, applications requiring high security generate the secret keys using PUFs. Due to the limited control over an FPGA fabric, it is challenging to design a PUF with 100% reliability. In this work, we propose a novel method of improving the reliability of an RO PUF under varying operating temperature. We first analyze the impact of temperature on the device characteristics that are responsible for variations in the RO frequency by using linear and non-linear regression methodologies. Later, we use this knowledge to correct the output response bit flips to improve reliability. Our proposed method is evaluated on a large dataset of 50 Xilinx 28nm Artix-7 XC7A35T FPGAs, each containing 6592 ROs at six different operating temperatures. Our experiments prove that we can correct the unreliable key back to a reliable one, thus achieving a higher reliability at different operating temperatures.

原文English
主出版物標題2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350334166
DOIs
出版狀態Published - 2023
事件2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan
持續時間: 17 4月 202320 4月 2023

出版系列

名字2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
國家/地區Taiwan
城市Hsinchu
期間17/04/2320/04/23

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