Layout-dependent effects (LDEs) introduce an inevitable performance degradation in analog and mixed-signal circuit design with advanced process technologies below 90 nm. The main LDE sources, including the well proximity effect (WPE), length of diffusion (LOD), and the oxide-to-oxide spacing effect (OSE), cause substantial fluctuations in carrier mobility and threshold voltage of transistors. In traditional design flows, impact of these in post-layout simulation, leading to expensive re-design iterations by inspecting the physical locations of devices with respect to one another. In this paper, we introduce the concept of an ideal mobility multiplier based on physics models, in order to minimize the LDE effects with a fast simulated annealing algorithm through various LDE alleviating operations. Based on the introduced mobility multiplier and hierarchical B*-tree (HB*-tree) topological representation, our LDE-aware analog placement methodology can simultaneously optimize not only the area and wire length, but also the LDEs, while maintaining linear-packing time complexity of HB*-trees. Compared to the most recent works on 65 nm-based analog circuits, experimental results show that the proposed method can effectively and efficiently reduce LDE variations, while improving circuit performance.
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|期刊||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|出版狀態||Accepted/In press - 2022|