Due to its excellent power efficiency, the successive-Approximation-register (SAR) analog-To-digital converter (ADC) is an attractive design choice for low-power ADC implements. In analog layout design, the parasitics induced by interconnecting wires and elements affect the accuracy and performance of the device. Due to the requirement of low-power and high-speed, the series of lateral metal-metal very small capacitor units as the architecture of capacitor array is usually adopted. Besides power consumption and area reduction, the parasitic capacitance would significantly affect the matching properties and setting time of capacitors. This work presents a framework to synthesize good-quality binary-weighted capacitors for custom advanced node planar SAR ADC. Also, this work proposed a parasitic-Aware ILP-based routing algorithm, which can generate an optimized layout considering parasitic capacitance and capacitance ratio mismatch simultaneously. The experimental result shows that the effective number of bits (ENOB) of the layout generated by our approach is comparable with manual design and other automated works.