On Generating Cell Library in Advanced Nodes: Efforts and Challenges

Hung Ming Chen; Cheng Li Hsiao; Wei Tung Chao; I. Chun Hsieh

doi:10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126

On Generating Cell Library in Advanced Nodes: Efforts and Challenges

Hung Ming Chen, Cheng Li Hsiao, Wei Tung Chao, I. Chun Hsieh

研究成果: Conference contribution › 同行評審

摘要

With the continuous progress of the manufacturing process, the related design rules become more and more complicated. In order to manufacture high complexity ICs, generating cell library in advanced nodes such as FinFET technology is intriguingly essential for fast circuit layout synthesis. This task was usually in manual process, not to mention in FinFET era. In this work, on top of other FinFET cell library generation works, we propose a methodology, including placement and routing of cells, to generate two cell libraries: ASAP7 PDK and 16nm leading foundry commercial node one. The efforts are presented, as well as the difficulties and challenges we encountered are depicted.

原文	English
主出版物標題	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9798350334166
DOIs	https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126
出版狀態	Published - 2023
事件	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan 持續時間: 17 4月 2023 → 20 4月 2023

出版系列

名字	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
國家/地區	Taiwan
城市	Hsinchu
期間	17/04/23 → 20/04/23

存取文件

10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126

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Link to publication in Scopus

引用此

Chen, H. M., Hsiao, C. L., Chao, W. T., & Hsieh, I. C. (2023). On Generating Cell Library in Advanced Nodes: Efforts and Challenges. 於 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126

Chen, Hung Ming ; Hsiao, Cheng Li ; Chao, Wei Tung 等. / On Generating Cell Library in Advanced Nodes : Efforts and Challenges. 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).

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title = "On Generating Cell Library in Advanced Nodes: Efforts and Challenges",

abstract = "With the continuous progress of the manufacturing process, the related design rules become more and more complicated. In order to manufacture high complexity ICs, generating cell library in advanced nodes such as FinFET technology is intriguingly essential for fast circuit layout synthesis. This task was usually in manual process, not to mention in FinFET era. In this work, on top of other FinFET cell library generation works, we propose a methodology, including placement and routing of cells, to generate two cell libraries: ASAP7 PDK and 16nm leading foundry commercial node one. The efforts are presented, as well as the difficulties and challenges we encountered are depicted.",

author = "Chen, {Hung Ming} and Hsiao, {Cheng Li} and Chao, {Wei Tung} and Hsieh, {I. Chun}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 ; Conference date: 17-04-2023 Through 20-04-2023",

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doi = "10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126",

language = "English",

series = "2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Chen, HM, Hsiao, CL, Chao, WT & Hsieh, IC 2023, On Generating Cell Library in Advanced Nodes: Efforts and Challenges. 於 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023, Hsinchu, Taiwan, 17/04/23. https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126

On Generating Cell Library in Advanced Nodes: Efforts and Challenges. / Chen, Hung Ming; Hsiao, Cheng Li; Chao, Wei Tung 等.
2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).

研究成果: Conference contribution › 同行評審

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T2 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023

AU - Chen, Hung Ming

AU - Hsiao, Cheng Li

AU - Chao, Wei Tung

AU - Hsieh, I. Chun

PY - 2023

Y1 - 2023

N2 - With the continuous progress of the manufacturing process, the related design rules become more and more complicated. In order to manufacture high complexity ICs, generating cell library in advanced nodes such as FinFET technology is intriguingly essential for fast circuit layout synthesis. This task was usually in manual process, not to mention in FinFET era. In this work, on top of other FinFET cell library generation works, we propose a methodology, including placement and routing of cells, to generate two cell libraries: ASAP7 PDK and 16nm leading foundry commercial node one. The efforts are presented, as well as the difficulties and challenges we encountered are depicted.

AB - With the continuous progress of the manufacturing process, the related design rules become more and more complicated. In order to manufacture high complexity ICs, generating cell library in advanced nodes such as FinFET technology is intriguingly essential for fast circuit layout synthesis. This task was usually in manual process, not to mention in FinFET era. In this work, on top of other FinFET cell library generation works, we propose a methodology, including placement and routing of cells, to generate two cell libraries: ASAP7 PDK and 16nm leading foundry commercial node one. The efforts are presented, as well as the difficulties and challenges we encountered are depicted.

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U2 - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126

DO - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126

M3 - Conference contribution

AN - SCOPUS:85163024264

T3 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

BT - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 17 April 2023 through 20 April 2023

ER -

Chen HM, Hsiao CL, Chao WT, Hsieh IC. On Generating Cell Library in Advanced Nodes: Efforts and Challenges. 於 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings). doi: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126

On Generating Cell Library in Advanced Nodes: Efforts and Challenges

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