@inproceedings{2b51fd90a81e48f78da21dc1afade0cb,
title = "On DRC Cleanness of Cell Porting for Design Migrations in Foundries and Technologies",
abstract = "Modern design migration needs fast turn-around time from one node to another to keep products competitive, including standard cell library generation. In such a scenario, we plan to preserve the original topology and inherit the original design intention, as well as predictable performance. Since the conventional handcrafted redesign of the standard cell library requires considerable engineering effort and design time, how to efficiently migrate/port the cell libraries with tedious design rules to follow become crucial. This work exploits the nature of DRC reports generated by the commercial DRC tool and presents an automatic standard cell layout migration framework to efficiently migrate cell library to be utilized in switching foundries and technologies. The experimental results show that the cell layout topology is well preserved in leading foundry 28nm technology and 0.18um automotive high voltage technology, and successfully reaching DRC cleanness.",
keywords = "cell layout, constraint graph, corner stitch, design rules, migration, standard cell",
author = "Wang, {Ching Ying} and Chen, {Chen Ho} and Chang, {Po Hsiang} and Hsieh, {Chien Yu} and Su, {Ching Feng} and Scott Ji and Liu, {Chien Nan Jimmy} and Chen, {Hung Ming}",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 ; Conference date: 22-04-2024 Through 25-04-2024",
year = "2024",
doi = "10.1109/VLSITSA60681.2024.10546349",
language = "English",
series = "2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings",
address = "美國",
}