On-chip voltage down converter for LV/LP digital system

Shyh-Jye Jou; Tsu Lin Chen

doi:10.1109/ISCAS.1997.621545

On-chip voltage down converter for LV/LP digital system

Shyh-Jye Jou^*, Tsu Lin Chen

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

4 引文斯高帕斯（Scopus）

摘要

A new on-chip differential amplifier based DC to DC Voltage Down Converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator, and high current drive capability. This VDC converts 5 V to lower voltage that the internal circuits of the chip are used. In here, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA), temperature dependency of 29 mv/°c. The VDC chip was fabricated in a 0.8 um Single-Poly-Double-Metal CMOS process and layout size is 690*210 μm². The output voltage is stabilized within ±1% for supply voltage with ±10% variation has been achieved.

原文	English
頁（從 - 到）	1996-1999
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621545
出版狀態	Published - 1 1月 1997
事件	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong 持續時間: 9 6月 1997 → 12 6月 1997

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10.1109/ISCAS.1997.621545

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@article{27383fb626bc44938e7e83b69e44c708,

title = "On-chip voltage down converter for LV/LP digital system",

abstract = "A new on-chip differential amplifier based DC to DC Voltage Down Converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator, and high current drive capability. This VDC converts 5 V to lower voltage that the internal circuits of the chip are used. In here, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA), temperature dependency of 29 mv/°c. The VDC chip was fabricated in a 0.8 um Single-Poly-Double-Metal CMOS process and layout size is 690*210 μm2. The output voltage is stabilized within ±1% for supply voltage with ±10% variation has been achieved.",

author = "Shyh-Jye Jou and Chen, {Tsu Lin}",

year = "1997",

month = jan,

day = "1",

doi = "10.1109/ISCAS.1997.621545",

language = "English",

volume = "3",

pages = "1996--1999",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 09-06-1997 Through 12-06-1997",

}

TY - JOUR

T1 - On-chip voltage down converter for LV/LP digital system

AU - Jou, Shyh-Jye

AU - Chen, Tsu Lin

PY - 1997/1/1

Y1 - 1997/1/1

N2 - A new on-chip differential amplifier based DC to DC Voltage Down Converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator, and high current drive capability. This VDC converts 5 V to lower voltage that the internal circuits of the chip are used. In here, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA), temperature dependency of 29 mv/°c. The VDC chip was fabricated in a 0.8 um Single-Poly-Double-Metal CMOS process and layout size is 690*210 μm2. The output voltage is stabilized within ±1% for supply voltage with ±10% variation has been achieved.

AB - A new on-chip differential amplifier based DC to DC Voltage Down Converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator, and high current drive capability. This VDC converts 5 V to lower voltage that the internal circuits of the chip are used. In here, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA), temperature dependency of 29 mv/°c. The VDC chip was fabricated in a 0.8 um Single-Poly-Double-Metal CMOS process and layout size is 690*210 μm2. The output voltage is stabilized within ±1% for supply voltage with ±10% variation has been achieved.

UR - http://www.scopus.com/inward/record.url?scp=0030648299&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.1997.621545

DO - 10.1109/ISCAS.1997.621545

M3 - Conference article

AN - SCOPUS:0030648299

SN - 0271-4310

VL - 3

SP - 1996

EP - 1999

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 9 June 1997 through 12 June 1997

ER -

On-chip voltage down converter for LV/LP digital system

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