On-chip voltage down converter for low-power digital system

Shyh-Jye Jou; Tsu Lin Chen

doi:10.1109/82.673644

On-chip voltage down converter for low-power digital system

Shyh-Jye Jou^*, Tsu Lin Chen

^*此作品的通信作者

電子研究所

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

摘要

An on-chip differential-amplifier-based dc-to-dc voltage down converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator and high current drive capability. VDC converts 5 V to lower voltage so that the internal circuits of the chip are used. In this paper, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 niA) and temperature dependency of 3.2 mV/°C. The VDC chip was fabricated in a 0.8-jum single-poly-double-metal CMOS process and layout size is 690210 -4im . The output voltage is stabilized within ±2.8% for supply voltage with ±10% variation achieved.

原文	English
頁（從 - 到）	617-625
頁數	9
期刊	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
卷	45
發行號	5
DOIs	https://doi.org/10.1109/82.673644
出版狀態	Published - 1 12月 1998

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AU - Chen, Tsu Lin

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AB - An on-chip differential-amplifier-based dc-to-dc voltage down converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator and high current drive capability. VDC converts 5 V to lower voltage so that the internal circuits of the chip are used. In this paper, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 niA) and temperature dependency of 3.2 mV/°C. The VDC chip was fabricated in a 0.8-jum single-poly-double-metal CMOS process and layout size is 690210 -4im . The output voltage is stabilized within ±2.8% for supply voltage with ±10% variation achieved.

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On-chip voltage down converter for low-power digital system

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