On-chip transient detection circuit for system-level ESD protection in CMOS ICs

Ming-Dou Ker*, Cheng Cheng Yen, Pi Chia Shih

*此作品的通信作者

    研究成果: Conference contribution同行評審

    5 引文 斯高帕斯(Scopus)

    摘要

    A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.

    原文English
    主出版物標題Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
    頁面361-364
    頁數4
    DOIs
    出版狀態Published - 2006
    事件IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
    持續時間: 10 9月 200613 9月 2006

    出版系列

    名字Proceedings of the Custom Integrated Circuits Conference
    ISSN(列印)0886-5930

    Conference

    ConferenceIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
    國家/地區United States
    城市San Jose, CA
    期間10/09/0613/09/06

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