On-chip memory module designs for video-signal processing

Tian-Sheuan Chang*, C. W. Jen

*此作品的通信作者

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

Two embedded memory designs are proposed for video-signal processing. Concurrent line access performs multiple-port memory accesses at the hardware cost and access time of a single port. It uses 62.24% of the area required by a conventional dual-port memory and is only 7.6% larger than a single-port 2K x 8 memory. The block-access mode combines address decoders and generators, yielding block-access mode times 26% faster than conventional schemes for a 256 words x 32 bits memory size. Despite some preferred-access-order restrictions, the designs incur no loss of generality because video algorithms possess high data parallelism and low dependence.

原文English
頁(從 - 到)138-144
頁數7
期刊IEE Proceedings: Circuits, Devices and Systems
144
發行號3
DOIs
出版狀態Published - 1 一月 1997

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