On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

Jie Ting Chen, Chun Yu Lin, Rong Kun Chang, Ming-Dou Ker*

*此作品的通信作者

研究成果: Article同行評審

13 引文 斯高帕斯(Scopus)

摘要

On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.

原文English
文章編號8501596
頁(從 - 到)5267-5274
頁數8
期刊IEEE Transactions on Electron Devices
65
發行號12
DOIs
出版狀態Published - 12月 2018

指紋

深入研究「On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process」主題。共同形成了獨特的指紋。

引用此