On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Ming-Dou Ker; Chung-Yu Wu; Tao Cheng; Michael J.N. Wu; Ta Lee Yu

doi:10.1109/ASIC.1995.580699

On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Ming-Dou Ker^*, Chung-Yu Wu, Tao Cheng, Michael J.N. Wu, Ta Lee Yu

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電子研究所

研究成果: Conference article › 同行評審

摘要

Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

原文	English
頁（從 - 到）	135-138
頁數	4
期刊	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.1995.580699
出版狀態	Published - 1 12月 1995
事件	Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA 持續時間: 18 9月 1995 → 22 9月 1995

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10.1109/ASIC.1995.580699

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abstract = "Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.",

author = "Ming-Dou Ker and Chung-Yu Wu and Tao Cheng and Wu, {Michael J.N.} and Yu, {Ta Lee}",

year = "1995",

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doi = "10.1109/ASIC.1995.580699",

language = "English",

pages = "135--138",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

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note = "Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 18-09-1995 Through 22-09-1995",

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T1 - On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Cheng, Tao

AU - Wu, Michael J.N.

AU - Yu, Ta Lee

PY - 1995/12/1

Y1 - 1995/12/1

N2 - Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

AB - Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

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U2 - 10.1109/ASIC.1995.580699

DO - 10.1109/ASIC.1995.580699

M3 - Conference article

AN - SCOPUS:0029542101

SN - 1063-0988

SP - 135

EP - 138

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit

Y2 - 18 September 1995 through 22 September 1995

ER -

On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

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