On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Ming-Dou Ker*, Chung-Yu Wu, Tao Cheng, Michael J.N. Wu, Ta Lee Yu

*此作品的通信作者

研究成果: Conference article同行評審

摘要

Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

原文English
頁(從 - 到)135-138
頁數4
期刊Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
出版狀態Published - 1 12月 1995
事件Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
持續時間: 18 9月 199522 9月 1995

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