TY - JOUR
T1 - On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology
AU - Ker, Ming-Dou
AU - Wu, Chung-Yu
AU - Cheng, Tao
AU - Wu, Michael J.N.
AU - Yu, Ta Lee
PY - 1995/12/1
Y1 - 1995/12/1
N2 - Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.
AB - Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.
UR - http://www.scopus.com/inward/record.url?scp=0029542101&partnerID=8YFLogxK
U2 - 10.1109/ASIC.1995.580699
DO - 10.1109/ASIC.1995.580699
M3 - Conference article
AN - SCOPUS:0029542101
SN - 1063-0988
SP - 135
EP - 138
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
T2 - Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit
Y2 - 18 September 1995 through 22 September 1995
ER -