On-chip ESD protection design for HV integrated circuits

Ming-Dou Ker*

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.

原文English
主出版物標題7th IEEE International Nanoelectronics Conference 2016, INEC 2016
發行者IEEE Computer Society
ISBN(電子)9781467389693
DOIs
出版狀態Published - 12 10月 2016
事件7th IEEE International Nanoelectronics Conference, INEC 2016 - Chengdu, China
持續時間: 9 5月 201611 5月 2016

出版系列

名字Proceedings - International NanoElectronics Conference, INEC
2016-October
ISSN(列印)2159-3523

Conference

Conference7th IEEE International Nanoelectronics Conference, INEC 2016
國家/地區China
城市Chengdu
期間9/05/1611/05/16

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