On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

C. Y. Chang*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Paper同行評審

    8 引文 斯高帕斯(Scopus)

    摘要

    ESD protection in RF integrated circuits has several considerations: low parasitic capacitance, constant input capacitance, and insensitive to substrate coupling noise. In this paper, a new ESD protection design with polysilicon diodes for RF IC applications is proposed and characterized. The proposed polysilicon diode is constructed by polysilicon layer in a general CMOS process with a central un-doped region. The polysilicon diode with variation on the width of the central un-doped region is characterized at different temperatures. An on-chip ESD protection circuit realized with the stacked polysilicon diodes to reduce the total input capacitance for GHz RF application is demonstrated.

    原文American English
    頁面240-243
    頁數4
    DOIs
    出版狀態Published - 4月 2001
    事件2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan
    持續時間: 18 4月 200120 4月 2001

    Conference

    Conference2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
    國家/地區Taiwan
    城市Hsinchu
    期間18/04/0120/04/01

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