On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

Tai Ho Wang*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Conference article同行評審

    7 引文 斯高帕斯(Scopus)

    摘要

    A novel on-chip ESD protection design by using polysilicon diodes for smart card application is reported in this paper. By adding an efficient VDD-to-VSS clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original approximately 300 V to become ≥3 kV. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing, the polysilicon diodes for both smart card application and on-chip ESD protection design.

    原文English
    文章編號890086
    頁(從 - 到)266-275
    頁數10
    期刊Electrical Overstress/Electrostatic Discharge Symposium Proceedings
    DOIs
    出版狀態Published - 26 9月 2000
    事件Electrical Overstress/Electrostatic Discharge Symposium Proceedings - Anaheim, CA, USA
    持續時間: 26 9月 200028 9月 2000

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