On-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs

Ming-Dou Ker; Chung-Yu Wu; Hsin Chin Jiang; Chung Yuan Lee; Joe Ko; Peter Hsue

doi:10.1109/MWSCAS.1994.519013

On-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs

Ming-Dou Ker^*, Chung-Yu Wu, Hsin Chin Jiang, Chung Yuan Lee, Joe Ko, Peter Hsue

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

摘要

A new on-chip ESD protection circuit with complementary SCR structures is proposed. This circuit can provide ESD protection above ±6500V and ±400V in human-body-mode and machine-mode ESD stresses, respectively, with the total layout area of 108μm × 242μm including the latchup guard-ring of 10 - μm width and a 90μm × 90μm metal pad for wire bonding.

原文	English
頁面	1145-1148
頁數	4
DOIs	https://doi.org/10.1109/MWSCAS.1994.519013
出版狀態	Published - 1 12月 1994
事件	Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2) - Lafayette, LA, USA 持續時間: 3 8月 1994 → 5 8月 1994

Conference

Conference	Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2)
城市	Lafayette, LA, USA
期間	3/08/94 → 5/08/94

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10.1109/MWSCAS.1994.519013

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Link to publication in Scopus

引用此

@conference{29eb1bfbc03d49da8041c1b5ea25c2f3,

title = "On-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs",

abstract = "A new on-chip ESD protection circuit with complementary SCR structures is proposed. This circuit can provide ESD protection above ±6500V and ±400V in human-body-mode and machine-mode ESD stresses, respectively, with the total layout area of 108μm × 242μm including the latchup guard-ring of 10 - μm width and a 90μm × 90μm metal pad for wire bonding.",

author = "Ming-Dou Ker and Chung-Yu Wu and Jiang, {Hsin Chin} and Lee, {Chung Yuan} and Joe Ko and Peter Hsue",

year = "1994",

month = dec,

day = "1",

doi = "10.1109/MWSCAS.1994.519013",

language = "English",

pages = "1145--1148",

note = "Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2) ; Conference date: 03-08-1994 Through 05-08-1994",

}

TY - CONF

T1 - On-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Jiang, Hsin Chin

AU - Lee, Chung Yuan

AU - Ko, Joe

AU - Hsue, Peter

PY - 1994/12/1

Y1 - 1994/12/1

N2 - A new on-chip ESD protection circuit with complementary SCR structures is proposed. This circuit can provide ESD protection above ±6500V and ±400V in human-body-mode and machine-mode ESD stresses, respectively, with the total layout area of 108μm × 242μm including the latchup guard-ring of 10 - μm width and a 90μm × 90μm metal pad for wire bonding.

AB - A new on-chip ESD protection circuit with complementary SCR structures is proposed. This circuit can provide ESD protection above ±6500V and ±400V in human-body-mode and machine-mode ESD stresses, respectively, with the total layout area of 108μm × 242μm including the latchup guard-ring of 10 - μm width and a 90μm × 90μm metal pad for wire bonding.

UR - http://www.scopus.com/inward/record.url?scp=0028758798&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.1994.519013

DO - 10.1109/MWSCAS.1994.519013

M3 - Paper

AN - SCOPUS:0028758798

SP - 1145

EP - 1148

T2 - Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2)

Y2 - 3 August 1994 through 5 August 1994

ER -

On-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs

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